Freescale Semiconductor MCF5480 - Manual (Page 174)

MCF548x Reference Manual, Rev. 3
5-8 Freescale Semiconductor
In addition, the following two privileged M68000 family instructions to load/store the USP are added to
the ColdFire instruction set architecture:
mov.l Ay,USP # move to USP: opcode = 0x4E6{0-7}
mov.l USP,Ax # move from USP: opcode = 0x4E6{8–F}
The address register number is encoded in the three low-order bits of the opcode.
These instructions are described in detail in
Section 5.7, “MMU Instructions .”
5.4.3 Access Error Stack Frame Additions
ColdFire exceptions generate a standard 2-longword stack frame, signaling the contents of the SR and PC
at the time of the exception, the exception type, and a 4-bit fault status field (FS). The first longword
contains the 16-bit format/vector word (F/V) and the 16-bit status register. The second contains the 32-bit
program counter address of the faulted instruction.
The FS field is used for access and address errors. To optimize TLB miss exception handling, new FS
encodings ( Table 5-2 ) allow quick error classification.
31 28 27 26 25 18 17 16 15 0
A7
→
FORMAT FS[3–2] VEC[7–0] FS[1–0] STATUS REGISTER
+ 0x04 PROGRAM COUNTER [31–0]
Figure 5-2. Exception Stack Frame
Table 5-2. Fault Status Encodings
FS[3:0] Definition
0000 Not an access or address error
0001, 001x Reserved
0100 Error (for example, protection fault) on instruction fetch
0101 TLB miss on opword of instruction fetch (New in CF4e)
0110 TLB miss on extension word of instruction fetch (New in CF4e)
0111 IFP access error while executing in emulator mode (New in CF4e)
1000 Error on data write
1001 Attempted write of protected space
1010 TLB miss on data write (New in CF4e)
1011 Reserved
1100 Error on data read
1101 Attempted read, read-modify-write of protected space (New in CF4e)
1110 TLB miss on data read, or read-modify-write (New in CF4e)
1111 OEP access error while executing in emulator mode (New in CF4e)