Freescale Semiconductor MCF5480 - Manual (Page 15)

MCF548x Reference Manual, Rev. 3
Freescale Semiconductor xv
Contents
Paragraph
Number
Title
Page
Number
9.3.1.4 JTAG Device Identification Number (JTAGID) .................................................... 9-5
Chapter 10
Internal Clocks and Bus Architecture
10.1 Introduction ................................................................................................................... 10-1
10.1.1 Block Diagram .......................................................................................................... 10-1
10.1.2 Clocking Overview ................................................................................................... 10-2
10.1.3 Internal Bus Overview .............................................................................................. 10-2
10.1.4 XL Bus Features ....................................................................................................... 10-3
10.1.5 Internal Bus Transaction Summaries ........................................................................ 10-3
10.1.6 XL Bus Interface Operations .................................................................................... 10-3
10.1.6.1 Basic Transfer Protocol ........................................................................................ 10-3
10.1.6.2 Address Pipelines .................................................................................................. 10-4
10.2 PLL ............................................................................................................................... 10-5
10.2.1 PLL Memory Map/Register Descriptions ................................................................. 10-5
10.2.2 System PLL Control Register (SPCR) ..................................................................... 10-5
10.3 XL Bus Arbiter ............................................................................................................. 10-6
10.3.1 Features ..................................................................................................................... 10-6
10.3.2 Arbiter Functional Description ................................................................................. 10-6
10.3.2.1 Prioritization ......................................................................................................... 10-6
10.3.2.2 Bus Grant Mechanism .......................................................................................... 10-7
10.3.2.3 Watchdog Functions ............................................................................................. 10-8
10.3.3 XLB Arbiter Register Descriptions .......................................................................... 10-8
10.3.3.1 Arbiter Configuration Register (XARB_CFG) .................................................... 10-9
10.3.3.2 Arbiter Version Register (XARB_VER) ............................................................ 10-10
10.3.3.3 Arbiter Status Register (XARB_SR) .................................................................. 10-11
10.3.3.4 Arbiter Interrupt Mask Register (XARB_IMR) ................................................. 10-11
10.3.3.5 Arbiter Address Capture Register (XARB_ADRCAP) ...................................... 10-13
10.3.3.6 Arbiter Bus Signal Capture Register (XARB_SIGCAP) ................................... 10-13
10.3.3.7 Arbiter Address Tenure Time Out Register (XARB_ADRTO) ......................... 10-14
10.3.3.8 Arbiter Data Tenure Time Out Register (XARB_DATTO) ............................... 10-15
10.3.3.9 Arbiter Bus Activity Time Out Register (XARB_BUSTO) ............................... 10-16
10.3.3.10 Arbiter Master Priority Enable Register (XARB_PRIEN) ................................. 10-16
10.3.3.11 Arbiter Master Priority Register (XARB_PRI) .................................................. 10-17
Chapter 11
General Purpose Timers (GPT)
11.1 Introduction ................................................................................................................... 11-1