9 rx fifo status register (pcirfsr) – Freescale Semiconductor MCF5480 User Manual
Page 528
MCF548x Reference Manual, Rev. 3
19-44
Freescale Semiconductor
19.3.3.2.9
Rx FIFO Status Register (PCIRFSR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
IP
TXW
0
0
0
0
0
0
FAE
RXW
UF
OF
FR
Full
Alarm Empty
W rwc
1
rwc
1
rwc
1
rwc
1
rwc
1
rwc
1
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x84C4
1
Bits 31, 30 and 23-20 are read-write-clear (rwc).
—Hardware can set rwc bits, but cannot clear them.
—Software can clear rwc bits that are currently set by writing a 1 to the bit location. Writing a 1 to a rwc bit that is currently
a 0 or writing a 0 to any rwc bit has no effect.
Figure 19-42. Rx FIFO Status Register (PCIRFSR)
Table 19-41. PCIRFSR Field Descriptions
Bits
Name
Description
31
IP
Illegal Pointer. An address outside the FIFO controller’s memory range has been written to one of
the user visible pointers. This bit will cause the FIFO error output to assert unless the IP_MASK bit
in the FIFO Controller register is set. Resetting the FIFO will clear this condition and the bit is cleared
by writing a one to it.
30
TXW
Transmit Wait Condition. Since the FIFO is configured as a Receive FIFO(ie. the PCI controller only
writes to this FIFO), this bit will not assert.
29–24
—
Reserved, should be cleared.
23
FAE
Frame accept error. This module does not support data framing functionality, so this bit should be
ignored.
22
RXW
Receive Wait Condition. This bit indicates that the FIFO is refusing to receive data from PCI because
there is not enough room in the FIFO to accept the data without causing overflow. This bit will cause
the error output to assert unless the RXW_MASK bit in the FIFO Control register is set. Resetting
the FIFO will clear this condition and the bit is cleared by writing a one to it.
21
UF
UnderFlow. This bit indicates that the read pointer has surpassed the write pointer. In other words
the FIFO has been read beyond Empty. Resetting the FIFO will clear this condition and the flag bit
is cleared by writing a one to it.
20
OF
OverFlow. This bit indicates that the write pointer has surpassed the read pointer. In other words
the FIFO has been written beyond Full. Resetting the FIFO will clear this condition and the flag bit
is cleared by writing a one to it.
19
FR
Frame Ready. The FIFO has a complete Frame of data ready for transmission. This module
does not provide support for data framing functionality, so this bit should be ignored.
18
Full
The FIFO is Full. This is not a sticky bit or error condition. The Full indication tracks with the state
of the FIFO.