Freescale Semiconductor MCF5480 - Manual (Page 954)

MCF548x Reference Manual, Rev. 3
30-24 Freescale Semiconductor
30.3.3.15 Group Address Upper Register (GAUR)
The GAUR is written by the user. This register contains the upper 32 bits of the 64-bit hash table used in
the address recognition process for receive frames with a multicast address. This register must be
initialized by the user.
30.3.3.16 Group Address Lower Register (GALR)
The GALR register is written by the user. This register contains the lower 32 bits of the 64-bit hash table
used in the address recognition process for receive frames with a multicast address. This register must be
initialized by the user.
Table 30-21. IALR Field Descriptions
Bits Name Description
31–0 IADDR2 Individual Address Lower - The lower 32 bits of the 64-bit hash table used in the address
recognition process for receive frames with a unicast address. Bit 31 of IADDR2 contains hash
index bit 31. Bit 0 of IADDR2 contains hash index bit 0.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R GADDR1
W
Reset Uninitialized
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R GADDR1
W
Reset Uninitialized
Reg
Addr
MBAR + 0x9120 (FEC0), 0x9920 (FEC1)
Figure 30-18. Group Address Upper Register (GAUR)
Table 30-22. GAUR Field Descriptions
Bits Name Description
31–0 GADDR1 Group Address Upper - GADDR1 contains the upper 32 bits of the 64-bit hash table used in the
address recognition process for receive frames with a multicast address. Bit 31 of GADDR1
contains hash index bit 63. Bit 0 of GADDR1 contains hash index bit 32.