Program counter breakpoint and mask registers (pbr – Freescale Semiconductor MCF5480 User Manual
Page 270
MCF548x Reference Manual, Rev. 3
8-20
Freescale Semiconductor
8.4.7
Program Counter Breakpoint and Mask Registers (PBRn, PBMR)
Each PC breakpoint register (PBR, PBR1, PBR2, PBR3) defines an instruction address for use as part of
the trigger. These registers’ contents are compared with the processor’s program counter register when the
appropriate valid bit is set, and TDR or XTDR are configured appropriately. PBR bits are masked by
setting corresponding PBMR bits. Results are compared with the processor’s program counter register, as
defined in TDR or XTDR. PBR1–PBR3 are not masked.
shows the PC breakpoint register.
PC breakpoint registers are accessible in supervisor mode using the WDEBUG instruction and through the
BDM port using the
RDMREG
and
WDMREG
commands using values shown in
.”
describes PBR, PBR1, PBR2, and PBR3 fields.
2
EAL1
Address enable bit: Enable address breakpoint low. The breakpoint is based on the address in the
ABLR. Trigger address = ABLR
1
EPC1
Enable PC breakpoint. If set, this bit enables the PC breakpoint for the first level trigger.
0
PCI1
Breakpoint invert. If set, this bit allows execution outside a given region as defined by
PBR/PBR1/PBR2/PBR3 and PBMR to enable a trigger. If cleared, the PC breakpoint is defined
within the region defined by PBR/PBR1/PBR2/PBR3 and PBMR.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
CNTRAD
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
CNTRAD
0
W
V
1
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
CPU + 0x08 (PBR); 0x18 (PBR1); 0x1A (PBR2); 0x1B (PBR3)
1
PBR0 does not have a valid bit. PBR0 is read as 0 and should be cleared.
Figure 8-11. Program Counter Breakpoint Registers (PBR, PBR1, PBR2, PBR3)
Table 8-12. TDR Field Descriptions (Continued)
Bits
Name
Description