4 rng interrupt status register (rngisr), Rng interrupt status register (rngisr) -48, P. 22-48 – Freescale Semiconductor MCF5480 User Manual
Page 650: Table 22-31, Describes rng status register fields
MCF548x Reference Manual, Rev. 3
22-48
Freescale Semiconductor
22.11.4 RNG Interrupt Status Register (RNGISR)
The RNG interrupt status register tracks the state of possible errors, if those errors are not masked, via the
RNG interrupt mask register. The definition of each bit in the interrupt status register is shown in
.
Figure 22-35. RNG Interrupt Status Register (RNGISR)
Table 22-31. RNGSR Field Descriptions
Bits
Name
Description
31-30
—
Reserved
29
HALT
Halt. Indicates that the RNG has halted due to an error.
0 RNG not halted
1 RNG halted
Note: Because the error causing the RNG to stop operating may be masked to the interrupt status
register, the status register is used to provide a second source of information regarding errors
preventing normal operation.
28
—
Reserved
27
OFR
Output FIFO Readable. The controller uses this signal to determine if the RNG can source the next
burst size block of data.
0 RNG output FIFO not ready
1 RNG output FIFO ready
26
IE
Interrupt Error. This status bit reflects the state of the ERROR interrupt signal, as sampled by the
controller interrupt status register (
Section 22.6.4.4, “SEC Interrupt Status Registers (SISRH and
”).
0 RNG is not signaling error
1 RNG is signaling error
25
—
Reserved
24
RD
Reset Done. This status bit, when high, indicates that the RNG has completed its reset sequence.
0 Reset in progress
1 Reset done
23-0
—
Reserved
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
ME
AE
0
0
0
0
OFU
0
0
0
0
IE
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x2E030