Freescale Semiconductor MCF5480 - Manual (Page 829)

Memory Map and Registers
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 27-11
27.6.4 DSPI Status Register (DSR)
The DSR contains status and flag bits. The bits reflect the status of the DSPI and indicate the occurrence
of events that can generate interrupt or DMA requests. Software can clear flag bits in the DSR by writing
a ‘1’ to it. Writing a ‘0’ to a flag bit has no effect.
0110 128 1110 32768
0111 256 1111 65536
Table 27-8. DSPI Baud Rate Scaler
BR Setting
Baud Rate
Scaler Value
BR Setting
Baud Rate
Scaler Value
0000 2 1000 256
0001 4 1001 512
0010 6 1010 1024
0011 8 1011 2048
0100 16 1100 4096
0101 32 1101 8192
0110 64 1110 16384
0111 128 1111 32768
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R TCF TXRXS 0 EOQF TFUF 0 TFFF 0 0 0 0 0 RFOF 0 RFDF 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R TXCTR TXPTR RXCTR RXPTR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reg
Addr
MBAR + 0x8A2C
Figure 27-5. DSPI Status Register (DSR)
Table 27-7. Scaler for CS to DSPISCK Delay, After DSPISCK Delay, and Delay After Transfer (Continued)
CSSCK / ASC / DT
Setting
PCS to DSPISCK
Delay Scaler Value
CSSCK / ASC / DT
Setting
PCS to DSPISCK
Delay Scaler Value