Freescale Semiconductor MCF5480 - Manual (Page 261)

Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 8-11
to guarantee that all accesses to these resources are serialized and logically consistent. The hardware
provides a locking mechanism in the CSR to allow the external development system to disable any
attempted writes by the processor to the breakpoint registers (setting IPW = 1). BDM commands must not
be issued if the ColdFire processor is accessing debug module registers with the WDEBUG instruction or
the resulting behavior is undefined.
The ColdFire debug architecture supports a number of hardware breakpoint registers, that can be
configured into single- or double-level triggers based on the PC or operand address ranges with an optional
inclusion of specific data values. With the addition of the MMU capabilities, the breakpoint specifications
must be expanded to optionally include the address space identifier (ASID) in these user-programmable
virtual address triggers.
The core includes four PC breakpoint triggers and two sets of operand address breakpoint triggers, each
with two independent address registers (to allow specification of a range) and a data breakpoint with
masking capabilities. Core breakpoint triggers are accessible through the serial BDM interface or written
through the supervisor programming model using the WDEBUG instruction.
Two ASID-related registers (PBAC and PBASID) are added for the PC breakpoint qualification, and two
existing registers (AATR and AATR1) are expanded for the address breakpoint qualification.
8.4.1 Revision A Shared Debug Resources
In the Revision A implementation of the debug module, certain hardware structures are shared between
BDM and breakpoint functionality, as shown in Table 8-7 .
Thus, loading a register to perform a specific function that shares hardware resources is destructive to the
shared function. For example, a BDM command to access memory overwrites an address breakpoint in
ABHR. A BDM write command overwrites the data breakpoint in DBR.
Revision B added hardware registers to eliminate these shared functions. The BAAR is used to specify bus
attributes for BDM memory commands and has the same format as the LSB of the AATR. Note that the
registers containing the BDM memory address and the BDM data are not program visible.
8.4.2 Configuration/Status Register (CSR)
The configuration/status register (CSR) defines the debug configuration for the processor and memory
subsystem and contains status information from the breakpoint logic. CSR is write-only from the
programming model. CSR is accessible in supervisor mode as debug control register 0x00 using the
WDEBUG instruction and through the BDM port using the RDMREG and WDMREG commands. It can
be read from and written to through the BDM port.
Table 8-7. Rev. A Shared BDM/Breakpoint Hardware
Register BDM Function Breakpoint Function
AATR Bus attributes for all memory commands Attributes for address breakpoint
ABHR Address for all memory commands Address for address breakpoint
DBR Data for all BDM write commands Data for data breakpoint