Freescale Semiconductor MCF5480 - Manual (Page 1020)

MCF548x Reference Manual, Rev. 3
Index-6 Freescale Semiconductor
Mechanical data
case drawing 31-20
diagram 31-8
pinout 31-1
Memory maps
debug 8-10
DMA 24-3
DSPI 27-4
EMAC 4-5
EPORT 14-2
Ethernet
control and status registers 30-7
MIB block counters 30-8
FlexCAN 21-5
I
2
C 28-3
interrupt controller 13-4
JTAG 23-4
MMU 5-11
PCI controller 19-4
PSC 26-3
SEC 22-8
SIU 9-1
SRAM 16-2
timers
CTM 25-3
GPT 11-2
SLT 12-1
USB 29-4
Message buffers
frames
overload 21-28
remote 21-27
self-received 21-25
handling 21-25
receive
codes 21-21
deactivation 21-26
error status flag (RXWARN) 21-17
serial 21-24
structure 21-19
time stamp 21-28
transmit
codes 21-22
deactivation 21-26
error status flag (TXWARN) 21-16
priority 21-24
MMU
access 5-4
access error 5-5, 5-8
architecture 5-1–5-3
cache addresses 5-4
effective address 5-9
hit determination 5-6
instructions 5-23
memory map 5-11
precise faults 5-4, 5-7
registers
base address (MMUBAR) 5-5, 5-10
control (MMUCR) 5-11
fault, test, or TLB address (MMUAR) 5-15
operation (MMUOR) 5-12
read/write tag and data entry (MMUTR,
MMUDR) 5-16
status (MMUSR) 5-14
stack pointers 5-5, 5-7
supervisor protection 5-7
TLB
address fields 5-20
general 5-18
locked entries 5-22
replacement algorithm 5-21
virtual mode 5-4
P
Pause frame 30-52
PCI arbiter
arbitration
examples 20-7
hidden bus 20-6
latency 20-7
scheme 20-6
interrupts 20-10
registers
control (PACR) 20-3
PCI controller
bus
protocol 19-48–??
interrupts 19-70
memory map 19-4
registers
base address 0 (PCIBAR0) 19-11
base address 1 (PCIBAR1) 19-12
cardbus CIS pointer (PCICCPR) 19-12
configuration 1 (PCICR1) 19-10
configuration 2 (PCICR2) 19-13
configuration address (PCICAR) 19-22
device ID/vendor ID (PCIIDR) 19-7
global status/control (PCIGSCR) 19-14
initiator control (PCIICR) 19-20
initiator status (PCIISR) 19-21
initiator window 0 base/translation address
(PCIIW0BTAR) 19-17
initiator window 1 base/translation address
(PCIIW1BTAR) 19-18