Freescale Semiconductor MCF5480 - Manual (Page 28)

MCF548x Reference Manual, Rev. 3
xxviii Freescale Semiconductor
Contents
Paragraph
Number
Title
Page
Number
23.2.1.3 Test Mode Select/Breakpoint (TMS/BKPT) ........................................................ 23-3
23.2.1.4 Test Data Input/Development Serial Input (TDI/DSI) ......................................... 23-3
23.2.1.5 Test Reset/Development Serial Clock (TRST/DSCLK) ...................................... 23-4
23.2.1.6 Test Data Output/Development Serial Output (TDO/DSO) ................................. 23-4
23.3 Memory Map/Register Definition ................................................................................ 23-4
23.3.1 Memory Map ............................................................................................................ 23-4
23.3.2 Register Descriptions ................................................................................................ 23-4
23.3.2.1 Instruction Shift Register (IR) .............................................................................. 23-4
23.3.2.2 IDCODE Register ................................................................................................. 23-4
23.3.2.3 Bypass Register .................................................................................................... 23-5
23.3.2.4 JTAG_CFM_CLKDIV Register ........................................................................... 23-5
23.3.2.5 TEST_CTRL Register .......................................................................................... 23-5
23.3.2.6 Boundary Scan Register ....................................................................................... 23-6
23.4 Functional Description .................................................................................................. 23-6
23.4.1 JTAG Module ........................................................................................................... 23-6
23.4.2 TAP Controller ......................................................................................................... 23-6
23.4.3 JTAG Instructions ..................................................................................................... 23-7
23.4.3.1 External Test Instruction (EXTEST) .................................................................... 23-8
23.4.3.2 IDCODE Instruction ............................................................................................. 23-8
23.4.3.3 SAMPLE/PRELOAD Instruction ......................................................................... 23-8
23.4.3.4 ENABLE_TEST_CTRL Instruction .................................................................... 23-9
23.4.3.5 HIGHZ Instruction ................................................................................................ 23-9
23.4.3.6 CLAMP Instruction .............................................................................................. 23-9
23.4.3.7 BYPASS Instruction ............................................................................................. 23-9
23.5 Initialization/Application Information .......................................................................... 23-9
23.5.1 Restrictions ............................................................................................................... 23-9
23.5.2 Nonscan Chain Operation ......................................................................................... 23-9
Chapter 24
Multichannel DMA
24.1 Introduction ................................................................................................................... 24-1
24.1.1 Block Diagram .......................................................................................................... 24-1
24.1.2 Overview ................................................................................................................... 24-2
24.1.2.1 Master DMA Engine (MDE) ................................................................................ 24-2
24.1.2.2 Address and Data Sequencer (ADS) ..................................................................... 24-2
24.1.2.3 Priority-Task Decoder (PTD) ............................................................................... 24-2
24.1.2.4 Logic Unit with Redundancy Check (LURC) ...................................................... 24-2
24.1.2.5 Debug Unit ............................................................................................................ 24-2
24.1.3 Features ..................................................................................................................... 24-2
24.2 External Signals ............................................................................................................ 24-3