Freescale Semiconductor MCF5480 - Manual (Page 437)

Functional Description
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 17-21
Figure 17-17 illustrates the longword write to a 32-bit device.
Figure 17-17. Longword Write Transfer with Muxed 32-A / 32-D
17.6.5.4 Timing Variations
The MCF548x has several features that can be used to change the timing characteristics of a basic read or
write bus cycle to provide additional address setup, address hold, and time for a device to provide or latch
data.
17.6.5.4.1 Wait States
Wait states can be inserted before each beat of a transfer by programming the CSCRn registers. Wait states
can be used to give the peripheral or memory more time to return read data or sample write data.
Figure 17-18 and Figure 17-19 show the basic read and write bus cycles (also shown in Figure 17-9 and
Figure 17-11 ). This is the default case with no wait states.
CLK
S0 S1 S2 S3
AD[31:24]
R/W
ALE
TA
OE
FBCSn, BE/BWEn
A[31:24] DATA[31:24]
AD[15:8] A[15:8] DATA[15:8]
AD[7:0] A[7:0] DATA[7:0]
AD[23:16] A[23:16] DATA[23:16]
TSIZ[1:0] 00