Freescale Semiconductor MCF5480 - Manual (Page 20)

MCF548x Reference Manual, Rev. 3
xx Freescale Semiconductor
Contents
Paragraph
Number
Title
Page
Number
18.3.13 SDR SDRAM Data Strobe (SDRDQS) .................................................................... 18-4
18.3.14 SDRAM Memory Supply (SDVDD) ........................................................................ 18-4
18.3.15 SDRAM Reference Voltage (VREF) ....................................................................... 18-4
18.4 Interface Recommendations ......................................................................................... 18-4
18.4.1 Supported Memory Configurations .......................................................................... 18-4
18.4.2 SDRAM SDR Connections ...................................................................................... 18-6
18.4.3 SDRAM DDR Component Connections .................................................................. 18-6
18.4.4 SDRAM DDR DIMM Connections ......................................................................... 18-7
18.4.5 DDR SDRAM Layout Considerations ..................................................................... 18-8
18.4.5.1 Termination Example ........................................................................................... 18-9
18.5 SDRAM Overview ....................................................................................................... 18-9
18.5.1 SDRAM Commands ................................................................................................. 18-9
18.5.1.1 Row and Bank Active Command (ACTV) ......................................................... 18-10
18.5.1.2 Read Command (READ) .................................................................................... 18-10
18.5.1.3 Write Command (WRITE) ................................................................................. 18-10
18.5.1.4 Precharge All Banks Command (PALL) ............................................................ 18-11
18.5.1.5 Load Mode/Extended Mode Register Command (LMR, LEMR) ...................... 18-11
18.5.1.6 Auto Refresh Command (REF) .......................................................................... 18-13
18.5.1.7 Self-Refresh (SREF) and Power-Down (PDWN) Commands ........................... 18-13
18.5.2 Power-Up Initialization ........................................................................................... 18-13
18.5.2.1 SDR Initialization ............................................................................................... 18-14
18.5.2.2 DDR Initialization .............................................................................................. 18-14
18.6 Functional Overview ................................................................................................... 18-15
18.6.1 Page Management ................................................................................................... 18-15
18.6.2 Transfer Size ........................................................................................................... 18-15
18.7 Memory Map/Register Definition .............................................................................. 18-16
18.7.1 SDRAM Drive Strength Register (SDRAMDS) .................................................... 18-17
18.7.2 SDRAM Chip Select Configuration Registers (CSnCFG) ..................................... 18-18
18.7.3 SDRAM Mode/Extended Mode Register (SDMR) ................................................ 18-19
18.7.4 SDRAM Control Register (SDCR) ......................................................................... 18-20
18.7.5 SDRAM Configuration Register 1 (SDCFG1) ....................................................... 18-21
18.7.6 SDRAM Configuration Register 2 (SDCFG2) ....................................................... 18-23
18.8 SDRAM Example ....................................................................................................... 18-24
18.8.1 SDRAM Signal Drive Strength Settings ................................................................ 18-25
18.8.2 SDRAM Chip Select Settings ................................................................................. 18-25
18.8.3 SDRAM Configuration 1 Register Settings ............................................................ 18-26
18.8.4 SDRAM Configuration 2 Register Settings ............................................................ 18-27
18.8.5 SDRAM Control Register Settings and PALL command ...................................... 18-27
18.8.6 Set the Extended Mode Register ............................................................................. 18-29
18.8.7 Set the Mode Register and Reset DLL ................................................................... 18-29
18.8.8 Issue a PALL command .......................................................................................... 18-30