2 floating-point instruction execution timing, Floating-point instruction execution timing -27 – Freescale Semiconductor MCF5480 User Manual

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Instructions

MCF548x Reference Manual, Rev. 3

Freescale Semiconductor

6-27

6.7.2

Floating-Point Instruction Execution Timing

Table 6-25

shows the ColdFire execution times for the floating-point instructions in terms of processor

core clock cycles. Each timing entry is presented as C(r/w).

•

C = The number of processor clock cycles including all applicable operand reads and writes plus

all internal core cycles required to complete instruction execution

•

r = The number of operand reads

•

w = The number of operand writes

NOTE

Timing assumptions are the same as those for the ColdFire ISA. See the

ColdFire Microprocessor Family Programmer’s Reference Manual.

OPMODE

Defines the exact operation to be performed by the FPU.

Defines the length of the PC-relative displacement for the FPU conditional branch
instruction. If SZ = 0, the displacement is 16 bits, otherwise a 32-bit displacement is used.

Specifies direction of the MOVE transfer. As a 0, it moves from memory to the FP; as 1, it
moves from the FP to memory.

LIST

Defines FPU data registers to be moved during the execution of the FMOVEM instruction.

REG SEL

Indicates the FPU control register to be moved during execution of an FMOVE control
register instruction.

Table 6-25. Floating-Point Instruction Execution Times

Opcode

Format

Effective Address

FPn

(An)

(An)+

-(An)

,An)

,PC)

FABS

y,FPx

1(0/0)

1(1/0)

FADD

y,FPx

4(0/0)

4(1/0)

FBcc

—

2(0/0) if correct,

9(0/0) if incorrect

FCMP

y,FPx

4(0/0)

4(1/0)

FDIV

y,FPx

23(0/0)

23(1/0)

FINT

y,FPx

4(0/0)

4(1/0)

FINTRZ

y,FPx

4(0/0)

4(1/0)

FMOVE

y,FPx

1(0/0)

1(1/0)

FPy,x

—

2(0/1)

—

y,FP*R

—

6(0/0)

6(1/0)

FP*R,x

—

1(0/0)

1(0/1)

—

Table 6-24. Instruction Format Terminology (Continued)

Term

Definition

This manual is related to the following products:

MCF5485 MCF5483 MCF5484 MCF5482 MCF5481