Freescale Semiconductor MCF5480 - Manual (Page 38)

MCF548x Reference Manual, Rev. 3
xxxviii Freescale Semiconductor
Contents
Paragraph
Number
Title
Page
Number
30.1.5.4 Internal Loopback ................................................................................................. 30-4
30.2 External Signals ............................................................................................................ 30-4
30.2.1 Transmit Clock (EnTXCLK) .................................................................................... 30-4
30.2.2 Receive Clock (EnRXCLK) ..................................................................................... 30-4
30.2.3 Transmit Enable (EnTXEN) ..................................................................................... 30-4
30.2.4 Transmit Data[3:0] (EnTXD[3:0]) ............................................................................ 30-4
30.2.5 Transmit Error (EnTXER) ........................................................................................ 30-5
30.2.6 Receive Data Valid (EnRXDV) ................................................................................ 30-5
30.2.7 Receive Data[3:0] (EnRXD[3:0]) ............................................................................. 30-5
30.2.8 Receive Error (EnRXER) ......................................................................................... 30-5
30.2.9 Carrier Sense (EnCRS) ............................................................................................. 30-5
30.2.10 Collision (EnCOL) .................................................................................................... 30-5
30.2.11 Management Data Clock (EnMDC) ......................................................................... 30-5
30.2.12 Management Data (EnMDIO) .................................................................................. 30-5
30.3 Memory Map/Register Definition ................................................................................ 30-6
30.3.1 Top Level Module Memory Map ............................................................................. 30-6
30.3.2 Detailed Memory Map (Control/Status Registers) ................................................... 30-7
30.3.3 MIB Block Counters Memory Map .......................................................................... 30-8
30.3.3.1 Ethernet Interrupt Event Register (EIR) ............................................................. 30-10
30.3.3.2 Interrupt Mask Register (EIMR) ........................................................................ 30-12
30.3.3.3 Ethernet Control Register (ECR) ........................................................................ 30-13
30.3.3.4 MII Management Frame Register (MMFR) ....................................................... 30-14
30.3.3.5 MII Speed Control Register (MSCR) ................................................................. 30-15
30.3.3.6 MIB Control Register (MIBC) ........................................................................... 30-17
30.3.3.7 Receive Control Register (RCR) ........................................................................ 30-17
30.3.3.8 Receive Hash Register (RHR) ............................................................................ 30-18
30.3.3.9 Transmit Control Register (TCR) ....................................................................... 30-19
30.3.3.10 Physical Address Low Register (PALR) ............................................................ 30-20
30.3.3.11 Physical Address High Register (PAHR) ........................................................... 30-21
30.3.3.12 Opcode/Pause Duration Register (OPD) ............................................................ 30-22
30.3.3.13 Individual Address Upper Register (IAUR) ....................................................... 30-22
30.3.3.14 Individual Address Lower Register (IALR) ....................................................... 30-23
30.3.3.15 Group Address Upper Register (GAUR) ............................................................ 30-24
30.3.3.16 Group Address Lower Register (GALR) ............................................................ 30-24
30.3.3.17 FEC Transmit FIFO Watermark Register (FECTFWR) .................................... 30-25
30.3.3.18 FEC Receive FIFO Data Register (FECRFDR) ................................................. 30-26
30.3.3.19 FEC Receive FIFO Status Register (FECRFSR) ................................................ 30-26
30.3.3.20 FEC Receive FIFO Control Register (FECRFCR) ............................................. 30-28
30.3.3.21 FEC Receive FIFO Last Read Frame Pointer Register (FECRLRFP) ............... 30-30
30.3.3.22 FEC Receive FIFO Last Write Frame Pointer Register (FECRLWFP) ............. 30-30
30.3.3.23 FEC Receive FIFO Alarm Register (FECRFAR) .............................................. 30-31