Freescale Semiconductor MCF5480 - Manual (Page 248)

MCF548x Reference Manual, Rev. 3
7-28 Freescale Semiconductor
The following tables present the same information as Table 7-7 , organized by the current state of the cache
line. In Table 7-8 the current state is invalid.
Table 7-7. Data Cache Line State Transitions
Access
Current State
Invalid (V = 0) Valid (V = 1, M = 0) Modified (V = 1, M = 1)
Read
miss (C,W)I1 Read line from
memory and update
cache;
supply data to
processor;
go to valid state.
(C,W)V1 Read new line from
memory and update
cache;
supply data to processor;
stay in valid state. CD1 Push modified line to buffer;
read new line from memory and
update cache;
supply data to processor;
write push buffer contents to
memory;
go to valid state.
Read hit (C,W)I2 Not possible. (C,W)V2 Supply data to processor;
stay in valid state. CD2 Supply data to processor;
stay in modified state.
Write
miss
(copy-
back) CI3 Read line from
memory and update
cache;
write data to cache;
go to modified state. CV3 Read new line from
memory and update
cache;
write data to cache;
go to modified state. CD3 Push modified line to buffer;
read new line from memory and
update cache;
write push buffer contents to
memory;
stay in modified state.
Write
miss
(write-
through) WI3 Write data to memory;
stay in invalid state. WV3 Write data to memory;
stay in valid state. WD3 Write data to memory;
stay in modified state.
Cache mode changed for the
region corresponding to this
line. To avoid this state, execute
a CPUSHL instruction or set
CACR[DCINVA,ICINVA] before
switching modes.
Write hit
(copy-
back) CI4 Not possible. CV4 Write data to cache;
go to modified state. CD4 Write data to cache;
stay in modified state.
Write hit
(write-
through) WI4 Not possible. WV4 Write data to memory and
to cache;
stay in valid state. WD4 Write data to memory and to
cache;
go to valid state.
Cache mode changed for the
region corresponding to this
line. To avoid this state, execute
a CPUSHL instruction or set
CACR[DCINVA,ICINVA] before
switching modes.
Cache
invalidate (C,W)I5 No action;
stay in invalid state.
(C,W)V5 No action;
go to invalid state. CD5 No action (modified data lost);
go to invalid state.
Cache
push (C,W)I6
(C,W)I7 No action;
stay in invalid state. (C,W)V6 No action;
go to invalid state. CD6 Push modified line to memory;
go to invalid state.
(C,W)V7 No action;
stay in valid state. CD7 Push modified line to memory;
go to valid state.