1 global status/control register (pcigscr), Global status/control register (pcigscr) -14 – Freescale Semiconductor MCF5480 User Manual
Page 498
MCF548x Reference Manual, Rev. 3
19-14
Freescale Semiconductor
registers are accessed primarily internally as offsets of MBAR, but can also be accessed by an external PCI
master if PCI base and target base address registers are configured to access the space. See
on configuring address windows.
19.3.2.1
Global Status/Control Register (PCIGSCR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
PE
SE
0
XLB2CLKIN
0
0
0
0
0
Reserved
W
rwc
1
rwc
1
Reset
0
0
0
0
0
—
2
0
0
0
0
0
Uninitialized
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
PEE
SEE
0
0
0
0
0
0
0
0
0
0
0
PR
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Reg
Addr
MBAR + 0xB60
1
Bits 29 and 28 are read-write-clear (rwc).
—Hardware can set rwc bits, but cannot clear them.
—Software can clear rwc bits that are currently set by writing a 1 to the bit location. Writing a 1 to a rwc bit that is
currently a 0 or writing a 0 to any rwc bit has no effect.
2
The reset value of bits 26-24 and 18-16 is determined by the PLL multiplier.
Figure 19-9. Global Status/Control Register (PCIGSCR)
Table 19-10.
PCIGSCR Field Descriptions
Bits
Name
Description
31–30
—
Reserved, should be cleared.
29
PE
PERR detected. This bit is set when the PCI Parity Error line, PCIPERR, asserts (any device). A
CPU interrupt will be generated if the PCIGSCR[PEE] bit is set. It is up to application software to
clear this bit by writing ‘1’ to it.
28
SE
SERR detected. This bit is set when a PCI System Error line, PCISERR, asserts (any device). A
CPU interrupt will be generated if the PCIGSCR[SEE] bit is set. It is up to application software to
clear this bit by writing ‘1’ to it.
27
—
Reserved, should be cleared.
26–24
XLB2CLKIN This bit field stores the XL bus clock to external PCI clock (CLKIN)divide ratio. This field is
read-only and the reset value is determined by the PLL multiplier (either 1, 2, or 4). Software can
read these bits to determine a valid ratio. If the register contains a differential value that does not
reflect the PLL settings, the PCI controller could malfunction.
23–19
—
Reserved, should be cleared.
18–16
CLKINReser
ved
This field is reserved.
15–14
—
Reserved, should be cleared.