4 slt status register (ssrn), Slt status register (ssrn) -4, 4 slt status register (ssr n ) – Freescale Semiconductor MCF5480 User Manual
Page 352
MCF548x Reference Manual, Rev. 3
12-4
Freescale Semiconductor
12.2.4
SLT Status Register (SSRn)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
0
0
0
0
BE
ST
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x90C (SSR0), + 0x91C (SSR1)
Figure 12-4. SLT Status Register (SSRn)
Table 12-5. SSRn Field Descriptions
Bits
Name Description
31–26
—
Reserved, should be cleared
25
BE
Bus Error Status. Provides information on attempted write to read-only register. The bit is
cleared by writing 1 to its bit position.
24
ST
SLT timeout. This status bit is set whenever the timer has expired. The bit is cleared by
writing 1 to its bit position. If interrupts are enabled, clearing this status bit also clears the
interrupt.
23–0
—
Reserved, should be cleared.