Freescale Semiconductor MCF5480 - Manual (Page 439)

Functional Description
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 17-23
Figure 17-20. Read Bus Cycle (One Wait State)
Figure 17-21. Write Bus Cycle (One Wait State)
17.6.5.4.2 Address Setup and Hold
The timing of the assertion and negation of the chip selects, byte selects, and output enable can be
programmed on a chip select basis. Each chip select can be programmed to assert one to four clocks after
address latch enable (ALE) is asserted. Figure 17-22 and Figure 17-23 show read and write bus cycles with
two clocks of address setup.
CLK
AD[X:0]
AD[31:Y]
R/W
ALE
TA
OE
S0 S1 WS S2 S3
FBCSn, BE/BWEn
ADDR[X:0]
A[31:Y] DATA
TSIZ[1:0] TSIZ[1:0]
CLK
AD[X:0]
AD[31:Y]
R/W
ALE
TA
OE
S0 S1 WS S2 S3
FBCSn, BE/BWEn
ADDR[X:0]
A[31:Y] DATA
TSIZ[1:0] TSIZ[1:0]