Freescale Semiconductor MCF5480 - Manual (Page 5)

MCF548x Reference Manual, Rev. 3
Freescale Semiconductor v
Contents
Paragraph
Number
Title
Page
Number
Chapter 1
Overview
1.1 MCF548x Family Overview ........................................................................................... 1-1
1.2 MCF548x Block Diagram .............................................................................................. 1-2
1.3 MCF548x Family Products ............................................................................................. 1-3
1.4 MCF548x Family Features ............................................................................................. 1-3
1.4.1 ColdFire V4e Core Overview ..................................................................................... 1-5
1.4.2 Debug Module (BDM) ................................................................................................ 1-6
1.4.3 JTAG ........................................................................................................................... 1-6
1.4.4 On-Chip Memories ..................................................................................................... 1-7
1.4.4.1 Caches ..................................................................................................................... 1-7
1.4.4.2 System SRAM ........................................................................................................ 1-7
1.4.5 PLL and Chip Clocking Options ................................................................................ 1-7
1.4.6 Communications I/O Subsystem ................................................................................ 1-8
1.4.6.1 DMA Controller ...................................................................................................... 1-8
1.4.6.2 10/100 Fast Ethernet Controller (FEC) ................................................................... 1-8
1.4.6.3 USB 2.0 Device (Universal Serial Bus) ................................................................. 1-8
1.4.6.4 Programmable Serial Controllers (PSCs) ............................................................... 1-9
1.4.6.5 I2C (Inter-Integrated Circuit) ................................................................................. 1-9
1.4.6.6 DMA Serial Peripheral Interface (DSPI) ................................................................ 1-9
1.4.6.7 Controller Area Network (CAN) .......................................................................... 1-10
1.4.7 DDR SDRAM Memory Controller ........................................................................... 1-10
1.4.8 Peripheral Component Interconnect (PCI) ............................................................... 1-10
1.4.9 Flexible Local Bus (FlexBus) ................................................................................... 1-10
1.4.10 Security Encryption Controller (SEC) ...................................................................... 1-11
1.4.11 System Integration Unit (SIU) .................................................................................. 1-11
1.4.11.1 Timers ................................................................................................................... 1-11
1.4.11.2 Interrupt Controller ............................................................................................... 1-12
1.4.11.3 General Purpose I/O ............................................................................................. 1-12
Chapter 2
Signal Descriptions
2.1 Introduction ..................................................................................................................... 2-1
2.1.1 Block Diagram ............................................................................................................ 2-1
2.2 MCF548x External Signals ........................................................................................... 2-16
2.2.1 FlexBus Signals ........................................................................................................ 2-16
2.2.1.1 Address/Data Bus (AD[31:0]) .............................................................................. 2-16
2.2.1.2 Chip Select (FBCS[5:0]) ....................................................................................... 2-17
2.2.1.3 Address Latch Enable (ALE) ................................................................................ 2-17