Freescale Semiconductor MCF5480 - Manual (Page 633)

ARC Four Execution Unit (AFEU)
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 22-31
22.8.4 AFEU Interrupt Status Register (AFISR)
The interrupt status register, seen in Figure 22-23 , tracks the state of possible errors, if those errors are not
masked via the AFEU interrupt mask register.
Figure 22-23. AFEU Interrupt Status Register (AFISR)
Table 22-20 describes AFEU interrupt status register fields.
25 ID Interrupt done. This status bit reflects the state of the DONE interrupt signal, as sampled by the
controller interrupt status register (
Section 22.6.4.4, “SEC Interrupt Status Registers (SISRH and
SISRL) ”).
0 AFEU is not signaling done
1 AFEU is signaling done
24 RD Reset done. This status bit, when set, indicates that AFEU has completed its reset sequence, as
reflected in the signal sampled by the appropriate crypto-channel.
0 Reset in progress
1 Reset done
23–0 — Reserved, should be cleared.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R ME AE OFE IFE 0 IFO OFU 0 0 0 0 IE ERE CE KSE DSE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reg
Addr
MBAR + 0x28030
Table 22-20. AFISR Field Descriptions
Bits Names Description
31 ME Mode error. An illegal value was detected in the mode register. Note: writing to reserved bits in mode
register is likely source of error.
0 No error detected
1 Mode error
30 AE Address error. An illegal read or write address was detected within the AFEU address space.
0 No error detected
1 Address error
Table 22-19. AFSR Field Descriptions (Continued)
Bits Name Description