Freescale Semiconductor MCF5480 - Manual (Page 356)

MCF548x Reference Manual, Rev. 3
13-4 Freescale Semiconductor
explicitly cleared in the interrupt service routine. This design provides unique vector capability for all
interrupt requests, regardless of the “complexity” of the peripheral device.
Vector number 64 is unused.
13.2 Memory Map/Register Descriptions
The register programming model for the interrupt controllers is memory-mapped to a 256-byte space. In
the following discussion, there are a number of program-visible registers greater than 32 bits in size. For
these control fields, the physical register is partitioned into two 32-bit values: a register “High” (the upper
longword) and a register “Low” (the lower longword). The nomenclature H and
L is used to reference these values.
The registers and their locations are defined in
Table 13-2 .
Table 13-2. Interrupt Controller Memory Map
Address
Offset
Name Byte0 Byte1 Byte2 Byte3 Access
0x700 Interrupt Pending Register High
[63:32]
IPRH R
0x704 Interrupt Pending Register Low
[31:0]
IPRL R
0x708 Interrupt Mask Register High
[63:32]
IMRH R/W
0x70c Interrupt Mask Register Low
[31:0]
IMRL R/W
0x710 Interrupt Force Register High
[63:32]
INTFRCH R/W
0x714 Interrupt Force Register Low
[31:0]
INTFRCL R
0x718 Interrupt Request Level Register
and Interrupt Acknowledge Level
and Priority Register
IRLR[7:1] IACKLPR Reserved R
0x71C–
0x73C
— Reserved —