Freescale Semiconductor MCF5480 - Manual (Page 1013)

MCF548x Reference Manual, Rev. 3
Freescale Semiconductor A-3
NOTE
Read and write accesses to reserved MBAR spaces will result in undefined
behavior that may result in a non-terminated bus cycle. This applies to the
reserved locations between modules and the reserved locations within valid
module address ranges.
MBAR + 0x1_FF00 –
0x1_FFFF
SRAMCFG 32KB System SRAM Configuration registers.
MBAR + 0x2_0000 –
0x3_FFFF
SEC Integrated Security Engine
Table A-1. MCF548x Module Memory Map Overview (continued)
Address
Name
(abbreviation)
Description