Table 29-37/29-36 – Freescale Semiconductor MCF5480 User Manual
Page 910
MCF548x Reference Manual, Rev. 3
29-36
Freescale Semiconductor
If a register write occurs at the same time an interrupt is received, the interrupt takes precedence over the
write.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Uninitialized
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
FU
EMT ERR FIFO
HI
FIFO
LO
0
EOT
0
EOF
W
Reset
Uninitialized
0
1
0
0
0
Unin.
0
Unin.
0
Reg
Addr
MBAR + 0xB444 (EP0ISR); 0xB474 (EP1ISR); 0xB4A4 (EP2ISR); 0xB4D4 (EP3ISR);
0xB504 (EP4ISR); 0xB534 (EP5ISR); 0xB564 (EP6ISR)
Figure 29-42. USB Endpoint n Interrupt Status Register (EPnISR)
Table 29-37. EPnISR Field Descriptions
Bits
Name
Description
31–9
—
Reserved, should be cleared.
8
FU
FIFO full. This is the FIFO full indicator. For OUT endpoints, this interrupt may assert in cases where
OUT packet data fills the FIFO and is subsequently discarded due to an incorrect CRC calculation.
Because of this, the FU bit in the FIFO status register (EPnFSR) should be checked to verify that
the OUT endpoint FIFO is actually full.
0 Indicates that the FIFO is not full.
1 Indicates that the FIFO is full.
7
EMT
FIFO empty. This is the FIFO empty indicator. For OUT endpoints, this interrupt may assert in cases
where OUT packet data is written to an empty FIFO and is subsequently discarded due to an
incorrect CRC calculation. Because of this, the EMT bit in the FIFO status register (EPnFSR) should
be checked to verify that the OUT endpoint FIFO is actually empty.
For IN endpoints, this interrupt may assert in cases where only one packet of data is stored in the
FIFO and that packet must be retried because it encounters an error while being sent to the host.
In this scenario, the FIFO will be temporarily empty before the retry operation causes the read
pointer to rewind. Thus, the EMT interrupt will set because of the temporary empty state of the FIFO.
Because of this, the EMT bit in the FIFO status register (EPnFSR) should be checked to verify that
the IN endpoint FIFO is actually empty.
0 Indicates that the FIFO is not empty.
1 Indicates that the FIFO is empty.
6
ERR
FIFO error. This indicates an error condition in the FIFO controller. The error condition can be
checked by reading the FIFO status register (EPnFSR).
0 No Error condition pending.
1 Error condition pending.
5
FIFOHI
FIFO high. This indicates that the number of bytes in the FIFO has surpassed the high level alarm
value.
4
FIFOLO
FIFO low. This indicates that the number of bytes in the FIFO has fallen below the FIFO low level
alarm value.