Displayed in, Figure 22-26 – Freescale Semiconductor MCF5480 User Manual
Page 638
MCF548x Reference Manual, Rev. 3
22-36
Freescale Semiconductor
Figure 22-26. DEU Status Register (DSR)
describes the DEU status register’s bit settings.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
HALT IFW
OFR
IE
ID
RD
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x2A028
Table 22-23. DSR Field Descriptions
Bits
Name
Description
31–30
—
Reserved
29
HALT
Halt. Indicates that the DEU has halted due to an error.
0 DEU not halted
1 DEU halted
Note: Because the error causing the DEU to stop operating may be masked to the interrupt status
register, the status register is used to provide a second source of information regarding errors
preventing normal operation.
28
IFW
Input FIFO Writable. The controller uses this signal to determine if the DEU can accept the next
burst size block of data.
0 DEU Input FIFO not ready
1 DEU Input FIFO ready
Note: The SEC implements flow control to allow larger than FIFO sized blocks of data to be
processed with a single key/IV. The DEU signals to the crypto-channel that a “burst size” amount of
space is available in the FIFO.
27
OFR
Output FIFO Readable. The controller uses this signal to determine if the DEU can source the next
burst size block of data.
0 DEU Output FIFO not ready
1 DEU Output FIFO ready
Note: The SEC implements flow control to allow larger than FIFO sized blocks of data to be
processed with a single key/IV. The DEU signals to the crypto-channel that a “burst size” amount of
data is available in the FIFO.
26
IE
Interrupt error. This status bit reflects the state of the ERROR interrupt signal, as sampled by the
controller interrupt status register (
Section 22.6.4.4, “SEC Interrupt Status Registers (SISRH and
0 DEU is not signaling error
1 DEU is signaling error