Freescale Semiconductor MCF5480 - Manual (Page 579)

Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 21-9
Table 21-3. CANCTRL Field Descriptions
Bits Name Description
31–24 PRESDIV Prescaler division factor. This 8-bit field defines the ratio between the system clock
frequency and the serial clock (S clock) frequency. The S clock period defines the time
quantum of the CAN protocol. For the reset value, the S clock frequency is equal to the
system clock frequency. The maximum value of this register is 0xFF, that gives a minimum
S clock frequency equal to the system clock frequency divided by 256. For more
information refer to
Section 21.4.9, “Bit Timing .”
23–22 RJW Resyncronization jump width. This 2-bit field defines the maximum number of time quanta
(one time quantum is equal to the S clock period) that a bit time can be changed by one
resynchronization. The valid programmable values are 0–3.
21–19 PSEG1 Phase buffer segment 1. This 3-bit field defines the length of phase buffer segment 1 in the
bit time. The valid programmable values are 0–7.
18–16 PSEG2 Phase buffer segment 2. This 3-bit field defines the length of phase buffer segment 2 in the
bit time. The valid programmable values are 0–7.
15 BOFFMSK Bus off mask. This bit provides a mask for the bus off interrupt.
0 Bus off interrupt disabled
1 Bus off interrupt enabled
14 ERRMSK Error mask. This bit provides a mask for the error interrupt.
0 Error interrupt disabled
1 Error interrupt enabled
13 — Reserved, should be cleared.
12 LPB Loop back. This bit configures FlexCAN to operate in loop-back mode. In this mode,
FlexCAN performs an internal loop back that can be used for self test operation. The bit
stream output of the transmitter is fed back internally to the receiver input. The Rx CAN
input pin is ignored and the Tx CAN output goes to the recessive state (logic 1). FlexCAN
behaves as it normally does when transmitting, and treats its own transmitted message as
a message received from a remote node. In this mode, FlexCAN ignores the bit sent during
the ACK slot in the CAN frame acknowledge field, generating an internal acknowledge bit
to ensure proper reception of its own message. Both transmit and receive interrupts are
generated.
0 Loop back disabled
1 Loop back enabled
11–8 — Reserved, should be cleared.
7 SAMP Sampling mode. The SAMP bit determines whether the FlexCAN module will sample each
received bit one time or three times to determine its value.
0 One sample, taken at the end of phase buffer segment 1, is used to determine the value
of the received bit.
1 Three samples are used to determine the value of the received bit. The samples are
taken at the normal sample point and at the two preceding periods of the S-clock; a
majority rule is used.
S clock frequency
f sys
PRESDIV + 1
------------------------------------ =
Resync jump width = (RJW + 1) time quanta
Phase buffer segment 1 (PSEG1 + 1) time quanta =
Phase buffer segment 2 (PSEG2 + 1)time quanta =