Freescale Semiconductor MCF5480 - Manual (Page 870)

MCF548x Reference Manual, Rev. 3
28-16 Freescale Semiconductor
/* Generate STOP by clearing I2CR.MSTA */
MCF_I2C_I2CR = 0x80;
}
/*Store received data and release SDA */
rx_buffer[i] = MCF_I2C_I2DR;
}
28.5.4 Generation of Repeated START
At the end of a data transfer, if the master still wants to communicate on the bus, it can generate another
START signal followed by another slave address without first generating a STOP signal. This is done by
writing a 1 to I2CR[MSTA].
28.5.5 Slave Mode
In the slave interrupt service routine, the addressed as slave bit (IAAS) should be tested to check if a calling
of its own address has just been received. If IAAS is set, software should set the transmit/receive mode
select bit (I2CR[MTX]) according to the R/W command bit (SRW). Writing to the control register clears
the IAAS automatically.
NOTE
Note that the only time IAAS is read as set is from the interrupt at the end
of the address cycle where an address match occurred; interrupts resulting
from subsequent data transfers will have IAAS cleared.
A data transfer may now be initiated by writing information to the data register, for slave transmits, or
dummy reading an address from the data register, in slave receive mode. The slave will drive SCL low in
between byte transfers; SCL is released when the data register is accessed in the required mode.
If the slave data register is not read after a transfer, the slave module will hold the SDA line low
indefinitely. The master is able to send a stop signal in this situation, but the slave does not respond by
releasing the SDA line. This functionality is a by-product of the arbitration scheme. To avoid this problem,
the slave data register must be read before a stop signal is issued.
In a slave transmitter routine, the received acknowledge bit (RXAK) must be tested before transmitting
the next byte of data. A dummy read of the last transmitted byte then releases the SCL line so that the
master can generate a STOP signal.
NOTE
Setting RXAK means an “end of data” signal from the master receiver, after
which the slave must be switched from transmitter mode to receiver mode
by software.
Following are examples of slave TX and RX illustrating the dummy read of I2DR and, for slave TX, the
checking of RXAK:
/************************************************************************
* Slave TX illustrating NACK on last byte (interrupt function disabled) *
*************************************************************************/