Freescale Semiconductor MCF5480 - Manual (Page 222)

MCF548x Reference Manual, Rev. 3
7-2 Freescale Semiconductor
• Physical location on the processor’s high-speed local bus with a user-programmed connection to
the internal instruction or data bus
• Memory location programmable on any 0-modulo-4K address boundary
• Byte, word, and longword address capabilities
• The RAM base address registers (RAMBAR0 and RAMBAR1) define the logical base address,
attributes, and access types for the two SRAM modules.
7.3 SRAM Operation
Each SRAM module provides a general-purpose memory block that the ColdFire processor can access
with single-cycle throughput. The location of the memory block can be specified to any 0-module-4K
address boundary in the 4-Gbyte address space by RAMBARn[BA], described in Section 7.4.1, “SRAM
Base Address Registers (RAMBAR0/RAMBAR1) .” The memory is ideal for storing critical code or data
structures or for use as the system stack. Because the SRAM module connects physically to the processor’s
high-speed local bus, it can service processor-initiated accesses or memory-referencing debug module
commands.
The Version 4e ColdFire processor core implements a Harvard memory architecture. Each SRAM module
may be logically connected to either the processor’s internal instruction or data bus. This logical
connection is controlled by a configuration bit in the RAM base address registers (RAMBAR0 and
RAMBAR1).
If an instruction fetch is mapped into the region defined by the SRAM, the SRAM sources the data to the
processor and any cache data is discarded. Likewise, if a data access is mapped into the region defined by
the SRAM, the SRAM services the access and the cache is not affected. Accesses from SRAM modules
are never cached, and debug-initiated references are treated as data accesses.
Note also that the SRAMs cannot be accessed by the on-chip DMAs. The on-chip system configuration
allows concurrent core and DMA execution, where the CPU can reference code or data from the internal
SRAMs or caches while performing a DMA transfer.
Accesses are attempted in the following order:
1. SRAM
2. Cache (if space is defined as cacheable)
3. System SRAM, MBAR space, or external access
7.4 SRAM Register Definition
The SRAM programming model consists of RAMBAR0 and RAMBAR1.
7.4.1 SRAM Base Address Registers (RAMBAR0/RAMBAR1)
The SRAM modules are configured through the RAMBARs, shown in Figure 7-1 . Each RAMBAR holds
the base address of the SRAM. The MOVEC instruction provides write-only access to this register from
the processor. Each RAMBAR can be read or written from the debug module in a similar manner. All
undefined RAMBAR bits are reserved. These bits are ignored during writes to the RAMBAR and return
zeros when read from the debug module. The valid bits, RAMBARn[V], are cleared at reset, disabling the
SRAM modules. All other bits are unaffected.
NOTE
RAMBARn is read/write by the debug module.