3 afeu status register (afsr), Afeu status register (afsr) -29, P. 22-29 – Freescale Semiconductor MCF5480 User Manual
Page 631
ARC Four Execution Unit (AFEU)
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
22-29
hardware reset, software reset, or module initialization, which performs proper initialization of the S-Box.
To determine when this is complete, observe the RD bit in the AFEU status register.
Figure 22-21. AFEU Reset Control Register (AFRCR)
describes AFEU reset control register fields.
22.8.3
AFEU Status Register (AFSR)
This status register, shown in
, contains 6 bits which reflect the state of the AFEU internal
signals. The AFEU status register is read-only. Writing to this location will result in address error being
reflected in the AFEU interrupt status register.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
0
0
0
RI
MI
SR
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x 21018
Table 22-18. AFRCR Field Descriptions
Bits Name
Description
31–27
—
Reserved, should be cleared.
26
RI
Reset interrupt. Writing this bit active high causes AFEU interrupts signalling DONE and
ERROR to be reset. It further resets the state of the AFEU interrupt status register.
0 Do not reset
1 Reset interrupt logic
25
MI
Module initialization is nearly the same as software reset, except that the interrupt control
register remains unchanged.
0 Do not reset
1 Reset most of AFEU
24
SR
Software reset is functionally equivalent to hardware reset (the RSTI pin), but only for the
AFEU. All registers and internal state are returned to their defined reset state. After the
reset completes, the AFEU will enter a routine to perform proper initialization of the S-Box.
0 Do not reset
1 Full AFEU reset
23-0
—
Reserved, should be cleared.