Freescale Semiconductor MCF5480 - Manual (Page 94)

MCF548x Reference Manual, Rev. 3
2-24 Freescale Semiconductor
2.2.6.5 AD2—Auto Acknowledge Configuration (AACONFIG)
At reset, the enabling and disabling of auto acknowledge for boot FBCS0 is determined by the logic level
driven on AD2 at the rising edge of RSTI. AACONFIG is multiplexed with AD2 and sampled only at reset.
The AD2 logic level is reflected as the reset value of CSCR0[AA]. Table 2-8 shows how the AD2 logic
level corresponds to the auto acknowledge timing for FBCS0 at reset. Auto acknowledge can be disabled
by driving a logic 0 on AD2 at reset.
2.2.6.6 AD[1:0]—Port Size Configuration (PSCONFIG)
The default port size value of the boot FBCS0 is determined by the logic levels driven on AD[1:0] at the
rising edge of RSTI, which are reflected as the reset value of CSCR0[PS]. Table 2-9 shows how the logic
levels of AD[1:0] correspond to the FBCS0 port size at reset.
2.2.7 Ethernet Module Signals
The following signals are used by the Ethernet module for data and clock signals.
2.2.7.1 Management Data (E0MDIO, E1MDIO)
The bidirectional EMDIO signals transfer control information between the external PHY and the
media-access controller. Data is synchronous to EMDC and applies to MII mode operation. This signal is
an input after reset. When the FEC operates in 10 Mbps 7-wire interface mode, this signal should be
connected to V
SS
.
Table 2-7. AD3/BECONFIG, BE/BWE[3:0] Boot Configuration
AD3 Boot FBCS0 Byte Strobe Configuration
0 BE[3:0] can assert for both read and write cycles.
1 BWE[3:0] are not asserted for reads;
BWE[3:0] only assert for write cycles
Table 2-8. AD2/AA_CONFIG Selection of FBCS0 Automatic Acknowledge
AD2 Boot FBCS0 AA Configuration at Reset
0 Disabled
1 Enabled with 63 wait states
Table 2-9. AD[1:0]/PSCONFIG[1:0] Selection of FBCS0 Port Size
AD[1:0] Boot FBCS0 Port Size
00 32-bit port
01 8-bit port
1X 16-bit port