Freescale Semiconductor MCF5480 - Manual (Page 370)

MCF548x Reference Manual, Rev. 3
14-4 Freescale Semiconductor
14.3.2.3 Edge Port Interrupt Enable Register (EPIER)
14.3.2.4 Edge Port Data Register (EPDR)
Table 14-3. EPDDR Field Descriptions
Bits Name Description
7–1 EPDDn Setting any bit in the EPDDR configures the corresponding pin as an output. Clearing any bit in
EPDDR configures the corresponding pin as an input. Pin direction is independent of the level/edge
detection configuration. Reset clears EPDD7–EPDD1.
To use an EPORT pin as an external interrupt request source, its corresponding bit in EPDDR must
be clear. Software can generate interrupt requests by programming the EPORT data register when
the EPDDR selects output.
0 Corresponding EPORT pin configured as input
1 Corresponding EPORT pin configured as output
0 — Reserved, should be cleared.
7 6 5 4 3 2 1 0
R EPIE7 EPIE6 EPIE5 EPIE4 EPIE3 EPIE2 EPIE1 0
W
Reset 0 0 0 0 0 0 0 0
Reg
Addr
MBAR + 0xF05
Figure 14-4. EPORT Port Interrupt Enable Register (EPIER)
Table 14-4. EPIER Field Descriptions
Bits Name Description
7–1 EPIEn Edge port interrupt enable bits enable EPORT interrupt requests. If a bit in EPIER is set, EPORT
generates an interrupt request when:
• The corresponding bit in the EPORT flag register (EPFR) is set or later becomes set.
• The corresponding pin level is low and the pin is configured for level-sensitive operation.
Clearing a bit in EPIER negates any interrupt request from the corresponding EPORT pin. Reset
clears EPIE7–EPIE1.
0 Interrupt requests from corresponding EPORT pin disabled
1 Interrupt requests from corresponding EPORT pin enabled
0 — Reserved, should be cleared.
7 6 5 4 3 2 1 0
R EPD7 EPD6 EPD5 EPD4 EPD3 EPD2 EPD1 0
W
Reset 1 1 1 1 1 1 1 1
Reg
Addr
MBAR + 0xF08
Figure 14-5. EPORT Port Data Register (EPDR)