Intel CONTROLLERS 413808 - Manual (Page 84)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
84 Order Number: 317805-001US
2.6.1.2 Inbound Read Queue Structure
The inbound read queues are responsible for retrieving data from local memory and
returning it to the PCI bus in response to a read transaction initiated from a PCI master.
When operating in the conventional PCI mode, reads are handled as delayed
transactions. When operating in the PCI-X mode reads are handled as split
transactions. The address of the transactions are held in the ITQ. Up to 8 read requests
can be stored in the ITQ. The read data is returned through IRQ.
When operating in the conventional PCI mode, the IRQ holds data from four PCI bus
read transactions. The read request cycle on PCI latches the read command and the
address into the ITQ when the cycle is first initiated by the PCI master. The ATU internal
bus initiator interface takes the translated address and the command and performs a
read on the internal bus. Reads can be any of the PCI memory read command types
using the ATU inbound translation or an inbound configuration read using the specific
configuration cycle translation. The data from the read on the internal bus is stored in
the IRQ until the PCI master initiates a read cycle that matches the initial request cycle
in both command and address. Any data left in an IRQ after the delivery of a
completion cycle on PCI is flushed. This is possible since all internal bus memory is
considered prefetchable with no read side effects.
When operating in the PCI-X mode, the IRQ may hold data from up to four PCI bus read
transactions. The read request cycle on PCI latches the read command and the address
into the ITQ when the cycle is first initiated by the PCI master. The ATU internal bus
initiator interface takes the translated address and the command and performs a read
on the internal bus. Reads can be any of the PCI memory read command types using
the ATU inbound translation or an inbound configuration read using the specific
configuration cycle translation. Once read data is available in the IRQ, the ATU
generates one or more split completions to return read data to the PCI requester.
When operating in the conventional PCI mode, the exact amount of data (byte count)
read by the master state machine on the internal bus interface depends upon the read
command used and how much data the Internal Bus target device delivers. Table 10
shows the amount of data attempted to be read for the different memory read
commands for the ATU, when operating in the conventional PCI mode.
Internal bus error conditions override all prefetch amounts (i.e., a master-abort and
target-abort conditions).
Table 10. Inbound Read Prefetch Data Sizes
PCI Read Command Prefetch Size (Bytes)
Memory Read 4 to 32
Memory Read Line 4 to 128
Memory Read Multiple 4 to 1024