Intel CONTROLLERS 413808 - Manual (Page 160)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
160 Order Number: 317805-001US
2.14.18 Inbound ATU Upper Base Address Register 2 - IAUBAR2
This register contains the upper base address when decoding PCI addresses for
memory space (Memory Space Indicator in IABAR2 is clear) beyond 4 GBytes. Together
with the Translation Base Address this register defines the actual location the
translation function is to respond to when addressed from the PCI bus for addresses >
4GBytes (for DACs).
The programmed value within the base address register must comply with the PCI
programming requirements for address alignment. Refer to the PCI Local Bus
Specification, Revision 2.3 for additional information on programming base address
registers.
Note: When the Type indicator of IABAR2 is set to indicate 32 bit addressability, the IAUBAR2
register attributes are read-only. By default the IAUBAR2 register has read-only
attributes. Prior to changing the Type Indicator in the IABAR2 to support 32-bit
addressability, the IAUBAR2 must be written with zero unless it already contains zero.
Zero is the default value for IAUBAR2.
Table 44. Inbound ATU Upper Base Address Register 2 - IAUBAR2
Bit Default Description
31:0 00000H
Translation Upper Base Address 2 - Together with the Translation Base Address 2 these bits define the
actual location the translation function is to respond to when addressed from the PCI bus for addresses
> 4GBytes.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+024H