Intel CONTROLLERS 413808 - Manual (Page 251)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 251
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
3.3.3 Outbound Write Transaction
An outbound write transaction is initiated by the Intel XScale
®
processor
9
or by one of
the DMAs and is targeted at a PCI Express domain. The outbound write address and
write data are propagated from the 4138xx internal bus to a PCI Express Link through
the OPHQ and OPDQ, respectively.
The ATUs internal bus target interface claims the write transaction and forwards it to
the PCI Express Link. The data flow for an outbound write transaction on the internal
bus is summarized in the following statements:
• ATU internal bus target interface latches the address from the internal bus into the
OPHQ when that address is inside one of the outbound translate windows (see
Section 3.8 ) and the OPHQ is not full.
• When the OPHQ is full, the target interface signals a Retry on the internal bus to
the outbound cycle initiator.
• Once outbound address is latched, internal bus target interface stores write data
into the OPDQ until the internal bus transaction completes or the reaches a buffer
boundary.
• When the data is latched in a buffer in OPDQ, the outbound cycle is enabled for
transmission on the PCI Express Link.
The PCI interface is responsible for completing the outbound write transaction with the
PCI address translated from the OPHQ and the data in the OPDQ. The data flow for an
outbound write transaction on the PCI Express Link is summarized in the following
statements:
• Writes transactions is fragmented based on the Max_Payload_Size parameter. A
write issues when the Max_Payload_Size is reached, or the write disconnects on
the internal bus.
• When Posted Header and Posted Data credits are available a memory write request
TLP is issued on the PCI Express Link.
• When a data parity error is detected while pulling data from the OPDQ, the TLP is
poisoned.
9. For best performance, the user should designate the two Outbound Memory Windows as
non-cachable and bufferable from the Intel XScale
®
processore. This assignment enables the
Intel XScale
®
processor to issue multiple outstanding transactions to the Outbound Memory
Windows, thereby, taking full advantage of the ATU outbound queue architecture. However, the
user needs to be aware that the Outbound ATU queue architecture does not maintain strict
ordering between read and write requests as described in Table 130, “ATU Outbound Data Flow
Ordering Rules” on page 265 . In the event that the user requires strict ordering to be maintained,
the user must change the designation of this region of memory to be
non-cachable/non-bufferable and enforce the requirement in software.