Intel CONTROLLERS 413808 - Manual (Page 640)

Intel ® 413808 and 413812—Timers
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
640 Order Number: 317805-001US
11.5 Uncommon TCRx and TRRx Conditions
Table 416 summarizes the most common settings for programming the timer registers.
Under certain conditions, however, it may be useful to set the Timer Count Register or
the Timer Reload Register to zero before enabling the timer. Table 427 details the
conditions and results when these conditions are set.
Table 427. Uncommon TMRx Control Bit Settings
TRRx TCRx
Bit 2
(TMRx.reloa
d)
Bit 1
(TMRx.enable
)
Action
X 0 0 1 TMRx.tc and TINTx set, TMR.enable cleared
0 0 1 1
Timer and auto reload enabled, TINTx not generated and timer
enable remains set.
0 N 1 1
Timer and auto reload enabled. TINTx set when TCRx=0. The
timer remains enabled but further TINTx’s are not generated.
Note: X = don’t care
N = a number between 1H and FFFF FFFFH