Intel CONTROLLERS 413808 - Manual (Page 643)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 643
SMBus Interface Unit—Intel ® 413808 and 413812
12.3.1 SMBus Controller
The 4138xx SMBus slave port interfaces to the configuration spaces of each ATU
function, and also interfaces to the memory-mapped registers. This gives SM (server
management) visibility into configuration space registers in the 4138xx ATUs 4138xx.
12.3.1.1 SMBus Commands
The 4138xx supports six SMBus commands:
Sequencing these commands initiates internal accesses to 4138xx configuration and
memory-mapped registers. For high reliability, 4138xx also supports the optional
Packet Error Checking feature (CRC-8) and is enabled or disabled with each
transaction.
Every configuration and memory read or write first consists of an SMBus write
sequence which initializes the Bus Number, Device, function number, memory address
offset etc. The term sequence is used since these variables can be initialized by the
SMBus master with a single block write or multiple word or byte writes. The last write in
the sequence that completes the initialization performs the internal
configuration/memory read or write. The SMBus master can then initiate a read
sequence which returns the status of the internal read or write command and also the
data in case of a read.
Each SMBus transaction has an 8-bit command driven by the master. The command
encodes the following information:
• Block Write • Word Write • Byte Write
• Block Read • Word Read • Bytes Read
Table 429. SMBus Command Encoding
Bit Description
7 Begin: The Begin bit when set indicates the first transaction of the read or write sequence.
6 End: The End bit when set indicates the last transaction of the read or write sequence.
5
Memory/Configure: Indicate whether memory or configuration space is being accesses in this SMBus
sequence. Value of ‘1’ indicates memory and a value of ‘0’ indicate configuration.
4
PEC Enable: Indicates that PEC is enabled when set. When set, each transaction in the sequence ends
with an extra CRC byte. 4138xx would check for CRC on writes and generate CRC on reads.
3:2
Internal Command:
00 — Read DWord
01 — Write Byte
10 — Write Word
11 — Write Dword
All access are naturally aligned to the access width. This field specifies the internal command to be
issued by the SMBus slave logic to the 4138xx
1:0
SMBus command:
00 — Byte
01 — Word
10 — Block
11 — Reserved
This field specifies the SMBus command to be issued on the SMBus. This field is used as an indication
of the length of transfer so that the slave knows when to expect the PEC packet (when enabled).