Intel CONTROLLERS 413808 - Manual (Page 252)

Intel
®
413808 and 413812—Address Translation Unit (PCI Express)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
252 Order Number: 317805-001US
3.3.4 Outbound Read Transaction
An outbound read transaction is initiated by the Intel XScale
®
processor
10
or one of the
DMAs and is targeted at a PCI slave on the PCI Express Link. The read transaction is
propagated through the outbound non posted queue (ONPQ) and read data is returned
through the inbound completion data queue (ICPLDQ).
The ATUs internal bus target interface claims the Memory Read transaction and
forwards the read request through to the PCI Express Link and returns the read data to
the internal bus.
The data flow for an outbound read transaction on the internal bus is summarized in
the following statements:
• The ATU internal bus interface latches the internal bus address when the address is
inside an outbound address translation window (or the direct addressing window,
when enabled) and the ONPQ is not full. All read transactions are handled as split
transactions. When the ONPQ is full (previous outbound transactions in progress),
the internal bus interface signals a Retry to the transaction initiator.
• Read requests is fragmented into sub-requests based on the
Max_Read_Request_Limit.
• When NPH credits are available, the ATU issue the read request when the head of
the ONPQ has at least one entry and the ordering rules are satisfied.
• Once the request is issued, the Transaction Pending bit is set in the “PCI Express
Device Status Register PE_DSTS” .
• When a Completion with Completion Status of UR or CA is encountered, a flag is set
and the ATU aborts the completion to the internal bus requester. The ONPQ is
cleared of the transaction.
• Completions for subsequent sub-request that are already issued is marked for
deletion and dropped once the completion returns.
• Once the transaction completes on the PCI Express Link, the ATU generates a
completion transaction to return data to the internal bus requester.
• Once all outstanding request are satisfied, the Transaction Pending bit is cleared in
the “PCI Express Device Status Register PE_DSTS”
10.For best performance, the user should designate the two Outbound Memory Windows as
non-cachable and bufferable from the Intel XScale
®
processor. This assignment enables the Intel
XScale
®
processor to issue multiple outstanding transactions to the Outbound Memory Windows,
thereby, taking full advantage of the ATU outbound queue architecture. However, the user needs
to be aware that the Outbound ATU queue architecture does not maintain strict ordering between
read and write requests as described in Table 130, “ATU Outbound Data Flow Ordering Rules” on
page 265 . In the event that the user requires strict ordering to be maintained, the user must
change the designation of this region of memory to be non-cachable/non-bufferable and enforce
the requirement in software.