Intel CONTROLLERS 413808 - Manual (Page 561)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 561
Peripheral Bus Interface Unit—Intel
®
413808 and 413812
9.3.8 PBI Drive Strength Control Register — PBDSCR
This register is used to manually control slew rate and drive strength for all of 4138xx
pins with the exception of high-speed serial interfaces, the SDRAM interface, and the
PCI-X interface.
Note: By default, this register is not required to program. This register should not be
programmed to a different value without consulting the 4138xx where the appropriate
values are specified.
Table 371. PBI Drive Strength Control Register — PBDSCR
Bit Default Description
31:20 000H Reserved
19:16 0011
2
Pull-Down Slew Rate Control (NSLW[3:0]): Tunes the slew rate of the n-drivers of all the pins with
the exception of the high speed serial interfaces, the SDRAM interface and the PCI-X interface.
15:12 0011
2
Pull-Up Slew Rate Control (PSLW[3:0]): Tunes the slew rate of the p-drivers of all the pins with the
exception of the high speed serial interfaces, the SDRAM interface and the PCI-X interface.
11:06 001100
2
Pull-Down Drive Strength (NDRV[5:0]): Programs the strength of the n-drivers of all the pins with
the exception of the high speed serial interfaces, the SDRAM interface and the PCI-X interface.
05:00 010110
2
Pull-Up Drive Strength (PDRV[5:0]): This field programs the strength of the p-drivers of all the pins
with the exception of the high speed serial interfaces, the SDRAM interface and the PCI-X interface.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor Local Bus Address offset
+2080H