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Intel CONTROLLERS 413808 User Manual

Page 122

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Intel

®

413808 and 413812—Address Translation Unit (PCI-X)

Intel

®

413808 and 413812 I/O Controllers in TPER Mode

Developer’s Manual

October 2007

122

Order Number: 317805-001US

Split Completion

Message

Correctable Data

Error (PCI-X)

None.

(PCI-X2)

ECCLOG Updated

Detected Correctable Error - bit

14

ATUIMR bit 11

Outbound Read

Request

Master-Abort

(All)

None.

(All)

Master Abort - bit 13

PCI Master Abort - bit 3

ATUIMR bit 5

(PCI-X and SCE) Received Split Completion Error

Message - bit 29

Received Split Completion Error

Message - bit 12

ATUIMR bit 9

Outbound Write

Request

Master-Abort

(All)

None.

(All)

Master Abort - bit 13

PCI Master Abort - bit 3

ATUIMR bit 5

(MSI)

SERR#

Asserted - bit 14

SERR#

Asserted - bit 10

ATUIMR bit 6

(MSI)

N/A

SERR#

Detected - bit 4

ATUCR bit 9

(PCI-X and SCE) Received Split Completion Error

Message - bit 29

Received Split Completion Error

Message - bit 12

ATUIMR bit 9

Inbound Read

Completions

Master-Abort

(PCI-X)

None.

Inbound

Configuration

Write

Completion

Message

Master-Abort

(PCI-X)

None.

Outbound Read

Request

Target-Abort

(All)

None.

(All)

Target Abort (master) - bit 12

PCI Target Abort (master) - bit 2 ATUIMR bit 4

(PCI-X and SCE) Received Split Completion Error

Message - bit 29

Received Split Completion Error

Message - bit 12

ATUIMR bit 9

Outbound Write

Request

Target-Abort

(All)

None.

(All)

Target Abort (master) - bit 12

PCI Target Abort (master) - bit 2 ATUIMR bit 4

(MSI)

SERR#

Asserted - bit 14

SERR#

Asserted - bit 10

ATUIMR bit 6

(MSI)

N/A

SERR#

Detected - bit 4

ATUCR bit 9

(PCI-X and SCE) Received Split Completion Error

Message - bit 29

Received Split Completion Error

Message - bit 12

ATUIMR bit 9

Table 18. ATU Error Reporting Summary - PCI Interface (Sheet 4 of 5)

Error Condition

(Bus Mode

a

)

Bits Set in

ATU Status Register

(ATUSR

b

)

or

PCI-X Status Register

(PCIXSR

c

)

and/or

ECC Logging Registers

d

(ECCLOG)

Bits Set in

ATU Interrupt Status

Register (ATUISR)

Interrupt Mask Bit in

ATUIMR or ATUCR

PCI Bus Error Response (i.e., signal Target-Abort, signal Master-Abort etc.)