25 atu interrupt pin register - atuipr, Table 52. atu interrupt pin register - atuipr, 26 atu minimum grant register - atumgnt – Intel CONTROLLERS 413808 User Manual
Page 167: Table 53. atu minimum grant register - atumgnt, 25atu interrupt pin register - atuipr, 26atu minimum grant register - atumgnt, 52 atu interrupt pin register - atuipr, 53 atu minimum grant register - atumgnt, Atu minimum grant register, Atumgnt
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
October 2007
Developer’s Manual
Order Number: 317805-001US
167
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.14.25 ATU Interrupt Pin Register - ATUIPR
ATU Interrupt Pin Register bit definitions adhere to PCI Local Bus Specification,
Revision 2.3. This register identifies the interrupt pin the ATU and Messaging Unit
interface uses. The 4138xx is, a PCI single-function device and, as such, generates only
one interrupt output. The interrupt output is for the Messaging Unit on
INTA#
.
2.14.26 ATU Minimum Grant Register - ATUMGNT
ATU Minimum Grant Register bit definitions adhere to PCI Local Bus Specification,
Revision 2.3. This register specifies the burst period the device requires in increments
of 8 PCI clocks.
This register and the ATU Maximum Latency register are information-only registers
which the configuration uses to determine how often a bus master typically requires
access to the PCI bus and the duration of a typical transfer when it does acquire the
bus. This information is useful in determining the values to be programmed into the
bus master latency timers and in programming the algorithm to be used by the PCI bus
arbiter.
Table 52. ATU Interrupt Pin Register - ATUIPR
Bit
Default
Description
07:00
01H
Interrupt Used - A value of 01H signifies that the ATU interface unit uses
INTA#
as the interrupt pin.
PCI
IOP
Attributes
Attributes
7
4
0
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+03DH
Table 53. ATU Minimum Grant Register - ATUMGNT
Bit
Default
Description
07:00
80H
This register specifies how long a burst period the device needs in increments of 8 PCI clocks.
PCI
IOP
Attributes
Attributes
7
4
0
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+003EH