2 smbus controller byte count register - sm_bc, 3 smbus controller addr3 register - sm_addr3, 4 smbus controller addr2 register - sm_addr2 – Intel CONTROLLERS 413808 User Manual
Page 656: 2 smbus controller byte count register — sm_bc, 3 smbus controller addr3 register — sm_addr3, 4 smbus controller addr2 register — sm_addr2, 435 smbus controller byte count register — sm_bc, 436 smbus controller addr3 register — sm_addr3, 437 smbus controller addr2 register — sm_addr2
Intel
®
413808 and 413812—SMBus Interface Unit
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
656
Order Number: 317805-001US
12.4.2
SMBus Controller Byte Count Register — SM_BC
The SM_BC register indicates the number of bytes following the command field when
performing a write or when setting up for a read. The byte count is also used when
returning the data to indicate the following bytes including the status byte which is
returned prior to the data. Note that the byte count is only transmitted for block type
accesses on SMBus. SMBus word or byte accesses do not use the byte count register.
12.4.3
SMBus Controller ADDR3 Register — SM_ADDR3
The SM_ADDR3 register should be programmed with the Bus Number of the desired
configuration register. The Status Register should be checked to make sure that there is
not a command currently in progress, before writing to this register. Writing to this
register when the 'Busy' bit in the Status Register is asserted has indeterminate effects.
When accessing memory, the SM_ADDR3 register is ignored by 4138xx.
12.4.4
SMBus Controller ADDR2 Register — SM_ADDR2
This register should be programmed with the Device Number and Function Number of
the desired configuration register. The Status Register should be checked to make sure
that there is not a command currently in progress, before writing to this register.
Writing to this register when the 'Busy' bit in the Status Register is asserted has
indeterminate effects. When accessing memory, bits 0, 1 and 2 of the SM_ADDR2
register provides address bits [16,17,18] of the memory address offset. The upper 5
bits of SM_ADDR2 register are ignored by 4138xx.
Table 435. SMBus Controller Byte Count Register — SM_BC
Bit
Reset
Description
07:00
00H
Byte Count: Indicates the number of bytes to anticipate for block size transfers. Not used for byte and
word size transfers.
Table 436. SMBus Controller ADDR3 Register — SM_ADDR3
Bit
Reset
Description
07:00
00H
ADDR3: Indicates the bus number to access when accessing configuration registers. Not used with
memory access.
Table 437. SMBus Controller ADDR2 Register — SM_ADDR2
Bit
Reset
Description
07:03
00H
Device Number (DEV): Device number of device to access.
02:00
000
Function Number (FNC): Function number of device to access. For memory access, bit 0 represents bit
16 of the address offset.