Intel CONTROLLERS 413808 - Manual (Page 618)

Intel
®
413808 and 413812—Interrupt Controller Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
618 Order Number: 317805-001US
04 0
2
IMU Interrupt
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL3
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL3
03 0
2
ATU-E Error Interrupt
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL3
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL3
02 0
2
ATU-E Configuration Register Write Interrupt
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL3
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL3
01 0
2
ATU-E/Start BIST Interrupt
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL3
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL3
00 0
2
I 2 C Bus Interface 2 Interrupt
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL3
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL3
Table 406. FIQ Interrupt Source Register 3 — FINTSRC3 (Sheet 2 of 2)
Bit Default Description
Memory
Coprocessor
Attributes
Attributes
28 24 20 16 12 8 4 0 31
ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro
na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor Coprocessor
address
CP6, Page 7, Register 3