Intel CONTROLLERS 413808 - Manual (Page 433)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 433
Messaging Unit—Intel
®
413808 and 413812
4.7.24 Message Upper Address Register - Message_Upper_Address
The Message Upper Address register is set during system initialization when system
software wishes to place the MSI address location above the 4G address boundary.
When this register is set to a non-zero value, the 4138xx generates a dual address
cycle for the MSI write command and uses the contents of this register as the upper
32-bits of that address.
Note: Refer to the Peripheral Registers Chapter for the default internal bus address. This
register is part of the configuration space of the Address Translation Unit that is setup
as an endpoint.
Table 289. Message Upper Address Register - Message_Upper_Address
Bit Default Description
31:00 00000000H Message Upper Address - Upper 32 bits of a 64-bit PCI address. This value is set by system software.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
PCI Configuration Offset
A8H
Internal Bus Address Offset
0A8H