Intel CONTROLLERS 413808 - Manual (Page 606)

Intel
®
413808 and 413812—Interrupt Controller Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
606 Order Number: 317805-001US
16 0
2
Peripheral Performance Monitor Interrupt — when set, at least one of the programmable event counters
and/or the Global Time Stamp Counter contains an overflow condition. Application software identifies
the counter by reading the Event Monitoring Interrupt Status register (EMISR).
0 = Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL0
1 = Interrupting and steered to internal IRQ exception and unmasked by INTCTL0
15 0
2
ATU/Start BIST Interrupt — when set, the host processor has set the start BIST request in the
ATUBISTR register.
0 = Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL0
1 = Interrupting and steered to internal IRQ exception and unmasked by INTCTL0
14 0
2
ATU-E Inbound Message Interrupt — when set, the ATU has set the Inbound Vendor Message Received
bit in the ATUISR register.
0 = Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL0
1 = Interrupting and steered to internal IRQ exception and unmasked by INTCTL0
13 0
2
Reserved.
12 0
2
Messaging Unit Interrupt
0 = Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL0
1 = Interrupting and steered to internal IRQ exception and unmasked by INTCTL0
11 0
2
I 2 C Bus Interface 1 Interrupt
0 = Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL0
1 = Interrupting and steered to internal IRQ exception and unmasked by INTCTL0
10 0
2
I 2 C Bus Interface 0 Interrupt
0 = Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL0
1 = Interrupting and steered to internal IRQ exception and unmasked by INTCTL0
9 0
2
Timer 1 Interrupt
0 = Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL0
1 = Interrupting and steered to internal IRQ exception and unmasked by INTCTL0
8 0
2
Timer 0 Interrupt
0 = Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL0
1 = Interrupting and steered to internal IRQ exception and unmasked by INTCTL0
7 0
2
Reserved.
6 0
2
Watch Dog Timer Interrupt
0 = Not Interrupting or Not steered to internal IRQ exception or masked by INTCTL0
1 = Interrupting and steered to internal IRQ exception and unmasked by INTCTL0
5 0
2
Reserved.
4 0
2
Reserved.
3 0
2
Reserved.
2 0
2
Reserved.
1 0
2
Reserved.
0 0
2
Reserved.
Table 399. IRQ Interrupt Source Register 0 — IINTSRC0 (Sheet 2 of 2)
Bit Default Description
Memory
Coprocessor
Attributes
Attributes
28 24 20 16 12 8 4 0 31
ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro
na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor Coprocessor address
CP6, page 6, Register 0