Intel CONTROLLERS 413808 - Manual (Page 129)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 129
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.10.2.2 Writing Vital Product Data
Using the fields defined in the VPD Capabilities List Item, the 4138xx writes Vital
Product Data using the following sequence of events:
1. Host processor executes a configuration write of the VPD data to be written to the
VPDDR.
2. Host processor executes a configuration write of the VPD address to the VPDAR
with the Flag set.
3. An interrupt to the Intel XScale
®
processor is triggered and bit 17 of the ATUISR is
set. Meanwhile, the host processor polls the VPDAR register waiting for the Flag to
be cleared.
Warning:
When any configuration writes to either the VPDAR or the VPDDR occur prior to the Flag
being cleared, the results of the original write operation are unpredictable.
4. Using the VPD Address, the Intel XScale
®
processor writes the Vital Product Data
from the VPDDR to the VPD storage component (i.e., Flash Memory).
5. The Intel XScale
®
processor clears the VPD interrupt status bit in the ATUISR.
6. The Intel XScale
®
processor then clears the Flag in the VPDAR register.
7. When the host processor detects that the Flag has been cleared, the host processor
has been informed that the VPD write operation is complete.