Intel CONTROLLERS 413808 - Manual (Page 443)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 443
SRAM DMA Unit (SDMA)—Intel
®
413808 and 413812
5.3 Theory of Operation
To perform a DMA operation, the firmware writes to either the HostToLocal or
LocalToHost registers, depending on the direction of transfer. One DMA is underway in
each direction simultaneously.
Each SDMA channel provides a “single-shot” DMA capability, in other words, one DMA
operation at a time. There is no ability to queue multiple DMA requests in a given
channel.
Before programming any of the registers, firmware must ensure that the DMA channel
is not active by ensuring that all previous DMA operations have completed (for example
by reading the Interrupt Counter / Interrupt Acknowledge and comparing that against
the last DMA operation requested). Firmware then writes the Host Addresses, Local
Addresses, and the Byte Count. The firmware then sets the CHGO bit to start the DMA.
Upon completion of the DMA operation, the firmware receives an interrupt. Two
interrupts are associated with the SDMA, a Normal and an Error interrupt.
In either case the firmware reads the Interrupt Counter of the channel(s) it has
programmed. Note that because the HostToLocal and LocalToHost channels are
independent then when both have been programmed the firmware needs to read each
channel Interrupt Counter to determine which channel has completed its DMA.
After reading the Interrupt Counter, firmware writes that counter value back to the
Interrupt Acknowledge field in the same register. This clears the interrupt, and another
DMA on that channel is started.
Errors are indicated by flags within each channel Control/Status registers. Further
information on the errors is obtained by examining the ATU or XSI System Controller
error registers.