Intel CONTROLLERS 413808 - Manual (Page 591)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 591
Interrupt Controller Unit—Intel
®
413808 and 413812
10.7.9 Interrupt Control Register 0 — INTCTL0
The Interrupt Control register 0 is a 32-bit Coprocessor 6 control register used to
specify which of 32 interrupts are masked.
Table 391. Interrupt Control Register 0 — INTCTL0 (Sheet 1 of 2)
Bit Default Description
31 0
2
XINT7# Interrupt Mask
0 = Masked
1 = Not Masked
30 0
2
Reserved.
29 0
2
XINT5# Interrupt Mask
0 = Masked
1 = Not Masked
28 0
2
XINT4# Interrupt Mask
0 = Masked
1 = Not Masked
27 0
2
XINT3# Interrupt Mask
0 = Masked
1 = Not Masked
26 0
2
XINT2# Interrupt Mask
0 = Masked
1 = Not Masked
25 0
2
XINT1# Interrupt Mask
0 = Masked
1 = Not Masked
24 0
2
XINT0# Interrupt Mask
0 = Masked
1 = Not Masked
23:19 0
2
Reserved.
18 0
2
Intel XScale ® Processor Cache Interrupt Mask
0 = Masked
1 = Not Masked
17 0
2
Intel XScale ® Processor PMU Interrupt Mask
0 = Masked
1 = Not Masked
16 0
2
Peripheral Performance Monitor Interrupt Mask
0 = Masked
1 = Not Masked
15 0
2
ATU/Start BIST Interrupt Mask
0 = Masked
1 = Not Masked
Memory
Coprocessor
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor Coprocessor address
CP6, Page 4, Register 0