Intel CONTROLLERS 413808 - Manual (Page 168)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
168 Order Number: 317805-001US
2.14.27 ATU Maximum Latency Register - ATUMLAT
ATU Maximum Latency Register bit definitions adhere to PCI Local Bus Specification,
Revision 2.3. This register specifies how often the device needs to access the PCI bus in
increments of 8 PCI clocks.
This register and the Minimum Grant Register are information-only registers which the
configuration uses to determine how often a bus master typically requires access to the
PCI bus and the duration of a typical transfer when it does acquire the bus. This
information is useful in determining the values to be programmed into the bus master
latency timers and in programming the algorithm to be used by the PCI bus arbiter.
Table 54. ATU Maximum Latency Register - ATUMLAT
Bit Default Description
07:00 00H
Specifies frequency (how often) the device needs to access the PCI bus in increments of 8 PCI clocks. A
zero value indicates the device has no stringent requirement.
PCI
IOP
Attributes
Attributes
7 4 0
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+03FH