Intel CONTROLLERS 413808 - Manual (Page 69)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 69
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.2.2.2 Outbound Address Translation Windows
Inbound translation involves a programmable inbound translation window consisting of
a base and limit register and a value register for PCI to internal bus translation. The
outbound address translation windows use a similar methodology except that the
outbound translation window limit sizes are fixed in the 4138xx internal bus address
space; this removes the need for separate limit registers.
Figure 8 on page 69 illustrates the five outbound address translation windows.
Figure 8. Outbound Address Translation Windows
ATU
Outbound I/O Cycle
Translation Window
(Default)
1 0000 0000H
2 0000 0000H
0 0000 0000H
1 FFFF FFFFH
2 FFFF FFFFH
0 FFFB 0000H
0 FFFB FFFFH
Memory Window 0
Memory Window 1
Code / Data
I/O Window
4 Gbytes
64 Kbytes
0 FFFA FFFFH
External Memory
Note: Before Enabling Outbound transactions in the ATUCR, default base
locations for Memory Transactions can be changed in OUMBAR[0:3].
3 0000 0000H
3 FFFF FFFFH
Memory Window 2
4 0000 0000H
4 FFFF FFFFH
Memory Window 3
ATU
Outbound Memory
Translation Windows
(Default)
B6325-01