Intel CONTROLLERS 413808 - Manual (Page 14)

Intel
®
413808 and 413812—Contents
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
14 Order Number: 317805-001US
8.3.3 Error Correction and Detection ...............................................................519
8.3.3.1 ECC Generation.......................................................................520
8.3.3.2 ECC Generation for Partial Writes ..............................................521
8.3.3.3 ECC Checking .........................................................................522
8.3.3.4 Scrubbing ..............................................................................526
8.3.3.4.1 ECC Example Using the H-Matrix..................................... 526
8.3.3.5 ECC Disabled..........................................................................527
8.3.3.6 ECC Testing............................................................................527
8.3.4 Byte Parity Checking and Generation.......................................................528
8.3.4.1 Parity Generation ....................................................................529
8.3.4.2 Parity Checking.......................................................................530
8.3.4.3 Parity Disabled........................................................................530
8.3.4.4 Parity Testing .........................................................................530
8.4 ECC Interrupts/Error Conditions.........................................................................531
8.4.1 Single-Bit Error Detection ......................................................................532
8.4.2 Multi-bit Error Detection ........................................................................533
8.5 Parity Interrupts/Error Conditions ......................................................................534
8.6 Register Definitions..........................................................................................535
8.6.1 SRAM Base Address Register — SRAMBAR................................................536
8.6.2 SRAM Upper Base Address Register — SRAMUBAR ....................................536
8.6.3 SRAM ECC Control Register — SECR........................................................536
8.6.4 SRAM ECC Log Register — SELOGR.........................................................538
8.6.5 SRAM ECC Address Register — SEAR.......................................................540
8.6.6 SRAM ECC Context Address Register — SECAR .........................................540
8.6.7 SRAM ECC Test Register — SECTST.........................................................541
8.6.8 SRAM Parity Control and Status Register — SPARCSR................................542
8.6.9 SRAM Parity Address Register — SPAR.....................................................543
8.6.10 SRAM Parity Upper Address Register — SPUAR .........................................543
8.6.11 SRAM Memory Controller Interrupt Status Register — SMCISR....................544
9.0 Peripheral Bus Interface Unit......................................................................................545
9.1 Overview........................................................................................................546
9.2 Peripheral Bus Signals......................................................................................547
9.2.1 Address Signal Definitions......................................................................547
9.2.2 Data Signal Definitions ..........................................................................547
9.2.3 Control/Status Signal Definitions.............................................................547
9.2.4 Bus Width............................................................................................548
9.2.5 Detailed Signal Descriptions ...................................................................549
9.2.6 Flash Memory Support...........................................................................550
9.2.6.1 Flash Read Cycle.....................................................................551
9.2.6.2 Flash Write Cycle ....................................................................553
9.3 Register Definitions..........................................................................................554
9.3.1 PBI Control Register — PBCR..................................................................555
9.3.2 PBI Status Register — PBISR..................................................................555
9.3.3 Determining Block Sizes for Memory Windows ..........................................556
9.3.4 PBI Base Address Register 0 — PBBAR0...................................................557
9.3.5 PBI Limit Register 0 — PBLR0.................................................................558
9.3.6 PBI Base Address Register 1 — PBBAR1...................................................559
9.3.7 PBI Limit Register 1 — PBLR1.................................................................560
9.3.8 PBI Drive Strength Control Register — PBDSCR ........................................561
9.3.9 Processor Frequency Register - PFR.........................................................562
9.3.10 External Strap Status Register 0 — ESSTSR0............................................563
9.3.11 Unique ID Register 0 — UID0 .................................................................564
9.3.12 Unique ID Register 1 — UID1 .................................................................564
10.0 Interrupt Controller Unit ............................................................................................565