Intel CONTROLLERS 413808 - Manual (Page 779)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 779
Clocking and Reset—Intel ® 413808 and 413812
17.5 Reset Strapping Options
Note: See Datasheet and/or Design Guide for details on how to configure reset straps.
Table 518, “Reset Strap Signals” on page 780 details the reset strapping options that
are available to configure the component during reset. These straps are sampled and
the component operating mode is determined at the deassertion of the fundamental
reset. All the straps are sampled at the trailing edge of P_RST# and WARM_RST# ;
however, a subset of straps are sampled for other resets.
• P_RST# and WARM_RST#
Sample all straps at the deassertion of both P_RST# and WARM_RST# .
• PCI Express Hot Reset, Loopback, Disable Link, and Link Down
When operating as a PCI Express endpoint, the following straps are re-sampled at
the deassertion of the reset condition.
— DFSEL[2:0]
— CONTROLLER_ONLY#
— CFG_CYCLE_EN#
— HOLD_X0_IN_RST#
— HOLD_X1_IN_RST#
• Software Reset (Internal Bus reset, Core reset, and so on)
Software Resets do not initiate a re-sampling of the reset straps and do not change
the mode of operation of the component.